Samsung maps HBM5 and zHBM for faster accelerator memory

Samsung outlined an updated memory roadmap at SEMICON Taiwan 2026, putting HBM5 and zHBM at the center of its next-generation plans. HBM5 is targeting twice the performance and 20% higher performance per watt than HBM4E, along with a 20% reduction in thermal resistance. The design moves the base die from the 4 nm process used in HBM4 and HBM4E to Samsung’s in-house 2 nm node, with stack options expanding to 12, 16, and 20 layers.

Mass production of HBM5 is expected around 2028. Samsung also confirmed at the Hot Chips 2026 conference’s Advance Program that it is preparing to ship HBM4E memory at 16 Gbps per pin, while its current HBM4 ships at 11.7 Gbps per pin.

zHBM represents a larger architectural shift by stacking memory directly on top of the processor rather than placing it beside the accelerator. Samsung is targeting eight times the raw performance and three times the performance per watt of HBM4E, with thermal resistance reduced by 75-90%. The company showed the industry’s first zHBM concept models at FMS 2026 and expects to launch the architecture after 2029.

The roadmap reflects a broader push to rethink HBM layouts for AI and high-performance computing accelerators. NVIDIA recently announced NVHBM, a custom memory design that moves the memory controller into the HBM base die instead of keeping it on the compute die.