TSMC advances CoWoS-L packaging for larger chips

TSMC has reportedly set a baseline yield of about 98% for its current CoWoS advanced packaging, a level that supports designs with die area equivalent to 5.5 times the reticle limit, or about 858 mm². The capability allows 4,720 mm² worth of silicon to be packaged on CoWoS-L, with only 1-2% of packaged designs experiencing issues. CoWoS-L had already been shipping, but this year marks the first time a 5.5x reticle chip has been packaged at mass production scale.

The company is also preparing packages for designs up to 14x reticle size dies on a single package, corresponding to 12,012 mm² of silicon area using CoWoS or one of its variants. That technology is slated for 2029, when TSMC’s A13 node is expected to be in mass production. Designs beyond the 3x reticle limit require careful engineering because thermal warping can create mechanical issues, and TSMC is working with customers to address those challenges.