Micron drops plans to commercialize 4F² DRAM

Micron will not bring 4F² DRAM to market despite researching the design for around two decades and claiming to have invented it. Scott DeBoer, the company’s president and chief technology and products officer, disclosed the decision during a technology webinar on October 21. He said the approach adds cost and complexity while facing fundamental scaling limits at leading-edge nodes.

The design uses vertical channel transistors to reduce cell footprints by about a third compared with today’s 6F² layout. DeBoer argued that capacitor spacing, rather than cell footprint, limits practical density, calling the claimed advantage ‘a bit of a myth.’ Samsung and SK hynix are pursuing 4F² designs, while China’s CXMT says its first product using the architecture will be a server DDR5 RDIMM due by the end of this year.

Micron instead plans to continue scaling 6F², with its 1-delta node scheduled to ramp in Boise, Idaho, in the second half of 2027. The subsequent 1-epsilon node will move to wafer bonding. Development of 3D DRAM continues in parallel without a launch timeline, and Micron says adoption will depend on economics. The strategy carries competitive risk if rivals achieve low-cost production at scale, particularly as Micron expects memory supply to tighten further in 2027 and 2028.