AMD debuts Venice, MI455X and Helios rack

AMD opened Advancing AI 2026 at Moscone West in San Francisco with EPYC “Venice,” the first x86 server processor to enter volume production on TSMC’s 2-nanometer N2 process. The launch also introduced the Instinct MI455X accelerator and Helios, a rack-scale AI system, with Meta, Microsoft, Oracle and OpenAI already committing capacity.

Venice replaces the longtime FinFET era with gate-all-around nanosheet transistors and pairs Zen 6c compute with 16 DDR5 channels delivering up to 1.6 TB/s of memory bandwidth per socket. Helios combines 72 MI455X GPUs, Venice CPUs and Pensando Vulcano 800G NICs, reaching 31 TB of aggregate HBM4 and AMD-rated performance of 2.9 exaFLOPS FP4 inference and 1.4 exaFLOPS FP8 training in roughly 140 kW.

The rack uses UALink, an open interconnect co-founded by AMD, Microsoft, Broadcom, Cisco, Google, HPE, Intel and Meta in May 2024. Initial H2 2026 systems rely on UALink-over-Ethernet, with purpose-built switching silicon not expected until 2027, while Microsoft’s Azure Helios commitment adds early validation.

Availability remains constrained. All 2026 HBM4 production is allocated to hyperscalers, MI455X mass production is placed at Q2 2027, and enterprise buyers outside the named cloud customers are directed toward 2027 procurement or Oracle’s 50,000-GPU MI450 supercluster launching in Q3 2026. Standalone Venice systems are due in Q3 2026 on the new SP7 socket.