TSMC and Intel take different routes to larger AI chip packages

AI accelerators are growing primarily at the package level as manufacturers combine more compute dies, chiplets and high-bandwidth memory. Integrating these components closely shortens data paths and increases bandwidth, but creates tougher challenges in power delivery, cooling, manufacturing yield and cost. TrendForce expects TSMC’s CoWoS-L to remain the mainstream packaging solution through 2028, supported by its technological maturity and yield advantages.

CoWoS-L combines redistribution layers for broad signal and power routing with local silicon interconnects where dense connections are needed. This avoids extending expensive, high-density silicon routing across the entire package. NVIDIA and AMD accelerators already use the technology, while Microsoft and AWS are expected to adopt it in 2027.

Intel’s competing EMIB-T embeds small silicon bridges in the package substrate and adds through-silicon vias for vertical power delivery. Its showcased implementation supports a package size of 120mm×120mm and an interconnect bump pitch of 25 microns. Google is expected to adopt EMIB-T in 2027, while AWS is testing EMIB technology.

Both approaches make packaging an increasingly important part of system design rather than a final assembly step. Larger packages require coordinated electrical, thermal and mechanical engineering, alongside more precise bonding and testing. Vertical chip stacking offers greater integration density, but heat, power delivery, yield and development costs continue to limit its suitability for large-scale, high-power AI accelerators.