TSMC A14 node promises smaller SRAM cells

TSMC expects its A14 process to reduce the size of its 6T SRAM bitcell to 0.017 µm², a 19% reduction. SRAM bitcell size has remained around 0.021 µm² since the launch of the N5 5 nm process in 2020, even as transistor density in logic elements has increased. The planned reduction would end a prolonged period in which memory scaling has failed to keep pace with logic advances.

Pilot production is underway to assess the node’s viability and allow customers to evaluate how their designs perform in TSMC’s manufacturing environment. Early successes have supported progress toward risk production in 2027, followed by high-volume manufacturing in 2028. Those milestones depend on avoiding major yield or production problems. If no significant challenges arise next year, TSMC could bring the production schedule forward by a few months.