TSMC expands N2 and advanced packaging for AI chips

TSMC is accelerating manufacturing expansion to meet rising demand for AI accelerators, with simultaneous ramps of its N2 process technology across multiple fabs and larger investments in advanced packaging. The N2 process is described as TSMC’s 2nm-class technology and uses Gate-All-Around nanosheet transistors to improve performance, power efficiency and transistor density over prior nodes.

Volume production for N2 is slated for late 2025, positioning the node as a key foundation for future AI and high-performance computing chips. TSMC is also scaling CoWoS and SoIC capacity, two packaging technologies used to integrate high-bandwidth memory, logic dies and chiplets in dense accelerator designs.

CoWoS is growing at an 80% CAGR and SoIC at a 90% CAGR through 2027, reflecting their role in next-generation systems. Hardware teams are being urged to track the maturity and availability of N2, CoWoS and SoIC because delays or capacity constraints could affect product roadmaps, sourcing strategies, BOM costs and design options for companies including NVIDIA, AMD and Apple.