TSMC and Intel push advanced packaging race

Advanced packaging is becoming a critical part of the AI chip supply chain as chip designers move toward chiplet architectures. As process scaling becomes more expensive, designers are separating chips into multiple components and relying on high-bandwidth, low-latency interconnects to keep performance gains moving.

TSMC continues to expand CoWoS capacity while reportedly developing an “EMIB-like” approach. At 2026 OCP APAC Summit, TSMC said its 5.5x reticle size CoWoS is in volume production, with yields consistently topping 98% across multiple AI customer products and reaching as high as 99% in some cases. The company expects to scale beyond 14x reticle size by 2029.

Intel’s EMIB embeds a silicon bridge directly into the substrate, avoiding a full-size interposer and offering lower cost potential if yield stability is comparable. Intel has said EMIB-T will scale to more than 8x this year and beyond 12x by 2028, while CEO Lip-Bu Tan said the company is focused on high-volume production for customer ramps in 2027.

Taiwanese OSAT providers are also advancing 2.5D packaging. ASE says FOCoS delivers interconnect density roughly 50x that of traditional flip-chip packaging, and over 200x with FOCoS-Bridge, while SPIL has developed FOEB to embed silicon bridges within the RDL layer.