TSMC plans major CoWoS expansion as rivals gain demand

TSMC may double its chip-on-wafer-on-substrate capacity from 2026 levels in 2028 as demand for AI GPU packaging continues to outstrip supply. CoWoS remains a leading packaging technology for AI accelerators and is used by major customers including NVIDIA.

Analysts cited by Taiwanese media expect TSMC’s CoWoS capacity to reach 260,000 wafers per month by the end of 2028, compared with 130,000 wafers per month by the end of this year. The expansion is expected to focus on the company’s Arizona campus and AP7 facility in Taiwan. Chips made at the Arizona site currently have to be flown to Taiwan for packaging because TSMC’s packaging capacity is located there.

The shortage is also giving competing approaches more room in the market. Intel’s EMIB-T, which uses embedded bridges in an organic substrate rather than a silicon interposer, is seen as better suited to custom AI chips from companies such as Google and Amazon. Analysts estimate Intel’s EMIB-T capacity could reach between 15,000 and 20,000 wafers per month in 2027 and between 40,000 and 45,000 wafers per month in 2028 on a CoWoS-equivalent basis.