TSMC reportedly sticks with microbumps for HBM packaging

TSMC is reportedly delaying investment in hybrid bonding for HBM memory integration, choosing instead to continue relying on microbumps inside advanced chip packages. Hybrid bonding forms a permanent connection between silicon chips by directly bonding copper interconnections, eliminating traditional chip bumps and enabling tighter die stacking.

Current packaging approaches use chip solder bumps that are roughly 100 micrometers in size, while microbumps are approximately 20 micrometers. Hybrid bonding reduces this size to 1 micrometer, but TSMC is said to be preparing its supply chain for microbumps that are 5 micrometers in size to improve packaging performance.

South Korean and Japanese suppliers are reportedly working with TSMC on the smaller interconnects, with mass production of 5-micrometer microbumps expected in the second half of 2028. AMD’s 3D V-Cache uses hybrid bonding to place SRAM on top of logic, but TSMC reportedly plans to keep HBM memory integration on microbumps for now.