AMD targets Nvidia Rubin with MI455X as TSMC packaging demand rises

AMD has introduced its sixth-generation EPYC 9006 server CPU and Instinct MI455X GPU, positioning the portfolio for agentic AI, cloud, enterprise, and HPC workloads. EPYC Venice has entered volume production on TSMC’s advanced 2nm process technology, while MI455X uses TSMC 2nm and 3nm FinFET technologies.

Advanced packaging is central to the rollout. Tom’s Hardware notes that MI455X integrates 320 billion transistors, with Accelerator Complex Dies hybrid-bonded onto Fabric and Cache Dies and connected with 12 HBM4 stacks through TSMC’s CoWoS-L. Commercial Times says some high-end EPYC Venice models may adopt CoWoS-L at TSMC’s Kaohsiung Fab 22, with ramp expected in the second half of 2026.

Commercial Times says CoWoS-L capacity remains tight, with some Chip-on-Wafer orders expected to move to ASE as TSMC and OSAT providers expand capacity with visibility through 2027 and 2028. SoIC demand is also expected to rise from AMD’s MI450, MI455X, and future AI chips, with institutional investors estimating TSMC capacity at 15,000-20,000 wafers per month by the end of 2026 before doubling again by the end of 2027.

Against Nvidia Rubin, Wccftech reports MI455X moves to HBM4, raising memory capacity by 50% from 288GB on the MI350 series to 432GB, while bandwidth rises to 22.3 TB/s from 8 TB/s. Compute reaches up to 40 PFLOPs of FP4 and 20 PFLOPs of FP8, compared with Rubin’s 50 PFLOPs of FP4 and 17.5 PFLOPs of FP8. Commercial Times says Anthropic has committed to invest US$5 billion, with a first 1 GW phase expected online in the first half of 2027.