TSMC’s 2 nm node sees surge in tape-outs

TSMC’s 2 nm N2 process is gaining stronger customer traction than its prior leading-edge 3 nm N3 node, with Senior Vice President Kevin Zhang confirming that N2 has four times the number of tape-outs. The shift suggests many long-time TSMC customers have prioritized 2 nm chip designs over 3 nm node PDKs.

The increase is tied to TSMC’s first gate-all-around FET nanosheet transistor. With GAAFET, N2 delivers up to a 15% performance increase at the same power level, or up to a 30% power reduction at the same speed. The node also offers a transistor density increase of about 15%, enabling either smaller dies with similar functionality or larger designs with more performance.

TSMC began high-volume production of N2 in Q4 2025, but the 2 nm node now accounts for only 3% of revenue, compared with 30% for 3 nm and 33% for 5 nm. Customers named for N2 include AMD with EPYC ‘Venice’ server CPUs and Apple with A20 Pro chips for the iPhone 18 Pro series, with revenue expected to rise as more chips reach customers.