Intel’s 18A-P process targets Diamond Rapids performance gains

AI-scale workloads are increasing pressure on data center CPUs, where chipmakers must extract more performance from each transistor without exceeding fixed power budgets. Intel’s 18A-P process combines gate-all-around RibbonFET transistors with PowerVia backside power delivery, a pairing Intel has measured at roughly 30% higher operating frequency at low voltage on production x86 silicon.

The process marks the industry’s first transistor architecture shift since FinFET arrived in 2011. Intel plans to use the technology for Diamond Rapids, its next-generation Xeon processor platform aimed at high-demand IaaS and AI-scale workloads.

The focus is on translating transistor-level improvements into practical per-core frequency gains, the metric that determines how quickly a single thread runs. Intel is also highlighting four design levers intended to extend frequency gains into high-voltage, high-performance designs, along with advanced materials such as subtractive ruthenium interconnect and future z-dimension logic stacking as possible roadmap extensions.