TSMC works on packaging technology to rival Intel EMIB

TSMC is reportedly developing an advanced packaging technology designed to compete with Intel’s Embedded Multi-die Interconnect Bridge, known as EMIB. The effort is internally referred to as EMIB-like and comes as TSMC’s Chip-on-Wafer-on-Substrate packaging could risk losing some customers to Intel’s competing approach.

Taiwan’s Kinsus Interconnect Technology is expected to support the project by helping TSMC develop, scale, and manufacture the CoWoS alternative. TSMC currently offers CoWoS-S, CoWoS-L, and CoWoS-R, each using a different interconnect strategy for advanced chip designs.

CoWoS-S uses a full monolithic silicon interposer with TSVs for maximum routing density and performance. CoWoS-L replaces the full silicon sheet with a lower-cost organic base and localized silicon bridges for high-speed die-to-die communication, while CoWoS-R uses an organic copper/polymer RDL interposer that trades some signal attenuation and routing density for mechanical flexibility, scalability, and cost efficiency in large-die chips.