Nvidia pushes AI agents into chip engineering

Nvidia is positioning AI agents and accelerated computing as core infrastructure for semiconductor engineering, arguing that traditional design workflows cannot keep pace with rising chip complexity. Tim Costa, Nvidia’s vice president and general manager of computational engineering, said that by 2030 the industry is expected to produce 2 trillion chips and process about 41 million wafers a month, while advanced packages approach a trillion transistors.

The company is deploying its Arm-based Vera CV100 CPU across EDA workflows used to develop future CPUs and GPUs, including simulation, formal verification, and physical implementation. Early engineering testing showed Vera running Synopsys’ VCS and Cadence’s Jasper platforms at 1.5 times the performance of AMD’s Epyc Torrent systems, with Nvidia working with both vendors to optimize applications for Vera as it helps design Rosa, a next-generation CPU due in 2028.

Cadence and Synopsys are also pushing agentic design tools. Cadence says its AI Super Agents can run hundreds of simulations under engineer direction and complete in less than a day work that now requires five weeks, delivering 40-times faster Register-Transfer Level (RTL) validation cycles. Synopsys demonstrated a Fully Autonomous Design Verification Workflow using Nvidia’s Nemotron 3 Ultra model, Agent Toolkit, and OpenShell runtime, saying it can deliver validated RTL 50 times faster than other platforms.