Imec maps chip scaling to A3 by 2038

Imec’s latest semiconductor roadmap projects logic process technology reaching the A3 generation around 2038, with 3 angstrom-class (0.3nm) fabrication technologies on the horizon. The research group expects contact poly pitch to stop scaling aggressively after A10, forcing chipmakers to pursue density gains through new transistor structures, smaller standard cells, backside power delivery, and advanced lithography.

Gate-all-around nanosheet transistors are expected to remain viable through A10, while CFET architectures become a serious production candidate at A7 in 2033. CFET stacks n-type and p-type transistors vertically rather than placing them side by side, adding another path for logic scaling as conventional nanosheet designs approach practical limits. Imec also sees High-NA EUV arriving around A14 and Hyper-NA EUV potentially needed later for the A3 generation.

The roadmap reframes Moore’s Law around logic-cell area rather than only transistor dimensions. Future AI accelerators and CPUs are expected to combine logic, memory, optical I/O, power delivery, and packaging under a Heterogeneous Large-Scale Integration model, with imec’s Cross-Technology Co-Optimization framework aimed at coordinating performance, energy efficiency, thermal behavior, and memory across entire systems.