AI chip growth runs into packaging and wafer limits

AI accelerator supply is being constrained less by chip design than by manufacturing steps around it. Estimates show Nvidia remains far ahead in shipped AI compute, with data-center GPUs at ~2,100 / ~7,000 / ~11,500 / ~18,000 EFLOPS across 2024 / 2025 / 2026E / 2027E, while Google TPU, AWS Trainium, AMD Instinct and Huawei Ascend all scale quickly from smaller bases.

In the US-linked supply chain, the pressure points are TSMC’s CoWoS advanced packaging and HBM memory. TSMC raised 2026 capex to $60–64B and said packaging capacity is now limiting customers’ growth, even as leading-edge wafer capacity expands. Micron also described HBM demand as well above supply into 2028, with 16 long-term supply contracts totaling >$22B in commitments.

China faces a different constraint: SMIC’s advanced-node wafer capacity for Huawei Ascend chips. SMIC’s 2026 capex is largely unchanged at ~$8B, with only ~40,000 wafers/month of capacity expected to be added after ~50,000 in 2025. Huawei’s roadmap depends on SMIC expanding production using domestic tool alternatives while export controls keep advanced ASML lithography out of reach.