China’s 3D chip startups face packaging and software tests

China’s domestic GPU sector is pushing investors toward new AI chip architectures marketed around 3D stacking, near-memory computing, and in-memory computing. The market groups together three different approaches: reorganizing logic chiplets, expanding memory capacity, and vertically integrating compute with memory. TSMC’s SoIC, Intel’s Foveros, and AMD’s MI300 represent the logic chiplet path, while HBM, HBF, and 3D V-Cache focus on memory bandwidth, capacity, and cache hierarchy.

Chinese startups are concentrating on vertical compute-memory integration because access to advanced process nodes, HBM, and high-end packaging remains constrained. Overseas companies often combine advanced packaging with cutting-edge nodes like 3nm and 2nm, while Chinese efforts more often begin from mature nodes such as 7nm. The strategy aims to offset manufacturing gaps through architectural and integration choices rather than competing directly with memory giants and leading foundries.

Commercial viability depends on proving that higher bandwidth and shorter data paths improve token throughput, cost efficiency, and customer adoption. Heterogeneous stacking also creates engineering problems around thermal dissipation, warpage, stress, and yield, with 4 to 6 layers described as a more realistic scope for compute-memory stacks at this stage. Advanced packaging options are also fragmenting, with Intel’s EMIB-T for Google’s “Humufish” TPU project in the second half of 2027 reporting a validation yield rate of over 90%, while CoWoS remains dominant for flagship AI training chips.