Nvidia funds packaging expansion as chip bottleneck tightens

Nvidia is reportedly providing billions of dollars in financing to expand advanced AI chip-packaging capacity at Siliconware Precision Industries, a subsidiary of Taiwan’s ASE Technology. Reuters cited an industry executive familiar with the arrangement. The investment aims to ease manufacturing constraints threatening deliveries of high-performance processors.

TSMC dominates sophisticated packaging through its Chip-on-Wafer-on-Substrate technology, known as CoWoS. The process places processors and high-bandwidth memory on a shared base, enabling rapid data transfers essential for AI workloads. Limited capacity is prompting customers to seek alternatives. AMD has announced plans to invest more than $10 billion across Taiwan’s semiconductor ecosystem, including partnerships with ASE, Siliconware Precision Industries and Powertech Technology.

Packaging has become increasingly important as shrinking transistors grows more difficult and expensive. Modern GPUs and CPUs can combine 10 to 20 distinct chips in a package. Former Intel CEO Pat Gelsinger estimates advanced packaging could eventually represent as much as half of a chip’s total value.

Powertech is working with AMD and Broadcom on panel-level packaging, which uses rectangular panels rather than round silicon wafers to fit more units into each production run and reduce material waste. It also plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore, targeting production by 2028.