NVIDIA lays out RISC-V path for CUDA and NVLink Fusion

NVIDIA used Hot Chips 2026 to describe how RISC-V host CPUs could fit into its GPU platforms, focusing on CUDA and NVLink Fusion. CUDA currently splits applications between CPU and GPU software modules, with compute-intensive functions running on the GPU and sequential work remaining on the CPU. NVIDIA already supports Intel/AMD x86 and Arm host CPUs, and said RISC-V systems would need to meet server-focused specifications such as RVA23 profiles and the RISC-V Boot and Runtime Services specification.

Binary compatibility is a core requirement. NVIDIA pointed to RVA23 as a way to ensure key extensions are present across RISC-V processors, while ACPI support arrived through ACPI 6.6 in May 2025, followed by the RISC-V Boot and Runtime Services specification in August 2025. CUDA also depends on hardware-based PCIe I/O coherence and PCIe peer-to-peer communication to reduce cache-management overhead and avoid extra host-memory copies in multi-GPU systems.

NVLink Fusion adds further requirements for custom CPUs connecting into NVIDIA AI platforms. The company described NVLink C2C integration with CHI coherence, unified memory access between CPU and GPU, and a high-speed C2C interconnect with around 88 PCIe lanes, plus software such as DOCA and NCCL. SiFive was identified as the RISC-V-based NVLink Fusion CPU partner, underscoring NVIDIA’s view of RISC-V as a potential server CPU option alongside x86 and Arm.