AMD opens AI event with Venice CPU and Helios rack

AMD opened Advancing AI 2026 in San Francisco with EPYC “Venice,” Instinct MI450-series accelerators, and the Helios rack-scale AI system, presenting a complete data center stack built around Zen 6 CPUs, CDNA 5 GPUs, ROCm, and open-standard interconnects. Venice is described as the first x86 server processor to enter volume production on TSMC’s 2-nanometer process node, giving enterprise buyers a new server platform while Intel’s direct P-core Xeon response, Diamond Rapids, is not expected until mid-2027.

Helios combines 72 MI455X accelerators with EPYC Venice CPUs and Pensando Vulcano 800-gigabit-per-second (Gbps) network interface cards across a double-wide rack. AMD says the system delivers 31 terabytes (TB) of HBM4 memory, 1.4 petabytes per second (PB/s) of combined bandwidth, 2.9 exaFLOPS of FP4 inference compute, and 1.4 exaFLOPS of FP8 training performance, though independent MLPerf results have not yet been submitted.

Availability remains uneven. HBM4 supply for 2026 is reportedly allocated to hyperscale customers, with broader MI455X mass production placed at Q2 2027 by independent analysis. Oracle is expected to offer a public cloud supercluster powered by 50,000 AMD Instinct MI450 GPUs starting in Q3 2026, while standalone Venice CPU systems are expected in Q3 2026.

The software case centers on ROCm. AMD’s stack now has PyTorch 2.7.0 support and works with vLLM and SGLang, but CUDA-dependent teams still face gaps around TensorRT-LLM, FlashAttention 3, training performance, and custom kernel migration.