XCENA outlines MX1 memory architecture at Hot Chips 2026

XCENA presented the architecture and measured performance of MX1 during the Hot Chips 2026 Memory session, positioning the system as a computational CXL memory architecture for AI infrastructure. Harry Kim, the company’s Chief Product Officer, detailed how MX1 combines large-scale memory expansion, SSD-backed capacity and programmable near-memory computing in a single CXL Type 3 device.

The design targets pressure points emerging as AI models grow, including memory capacity limits, data movement and the cost dynamics of high-bandwidth memory scaling. MX1 is intended to complement CPUs, GPUs and AI accelerators by expanding available memory and offloading selected memory-bound tasks such as vector search, KV-cache retrieval and data preprocessing, allowing host processors to focus on compute-intensive inference.