IBM and Siemens collaborate on nanostack transistor research

IBM and Siemens are collaborating on research to advance IBM’s nanostack transistor architecture, unveiled earlier this year. The effort combines IBM’s semiconductor device expertise with Siemens’ capabilities in electronic design automation, process simulation, lithography optimization and advanced manufacturing software.

IBM describes nanostack as the industry’s first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors to increase chip density, packing nearly 100 billion transistors into a space the size of a fingernail at its current 7 angstrom node.

The architecture also allows different material combinations within each stacked layer, enabling the performance and power efficiency of each transistor to be optimized independently. These design features support improvements in energy efficiency, performance and SRAM scaling, with the collaboration intended to accelerate nanostack’s development.