Ayar Labs positions optical chiplets for AI data center bottleneck

Ayar Labs CEO Mark Wade says AI data centers are nearing a physical limit as electrical links struggle to connect GPUs and accelerators over longer distances at higher bandwidth. His core bet, developed over roughly 15 years, is that optical connectivity must move inside the compute package and be manufactured through leading-edge CMOS supply chains rather than treated as a telecom niche.

The company is building optical engines that combine a 3nm electrical IC made in TSMC COUPE with a photonics wafer process, advanced packaging and optical connectors. Wade frames the hardest remaining challenges as laser manufacturing and production test architecture, including how to bring photonics into wafer-scale testing, assembly and manufacturing economics.

Ayar has built a strategic investor base around the ecosystem, including Nvidia, AMD, Intel, TSMC and Wiwynn. It previously shipped a 2 Tbps chiplet, then a 4 Tbps chiplet, and later an 8 Tbps part to customer R&D labs, helping support institutional financing. The Series E earlier in 2026 was led by Newberger Berman, and Wiwynn’s investment brought $650 million year-to-date on the primary side.

Wade expects leading-edge GPU makers to deploy co-packaged optics in 2028-2029, followed by broader accelerator adoption in 2029-2031. Ayar is positioning for an IPO aligned with that deployment window, arguing that optical engines could become a capacity-constrained component similar to HBM in the next AI infrastructure cycle.