Rapidus pushes panel-level packaging roadmap toward 2030

Rapidus outlined an advanced packaging roadmap at the 2026 OCP APAC Summit, setting eight-reticle-size interposers and 600 x 600 mm panel-level processing as goals for around 2030. Rapidus Design Solutions CTO Rozalia Beica presented a progression from four reticles (3,320 mm²) to six (4,980 mm²) and eventually eight (6,640 mm²) by 2030, with the company emphasizing the yield advantages of moving to panel scale.

Beica compared output for an eight-reticle interposer across formats: four units on a standard 300 mm wafer, nine on a 300 x 300 mm panel, 36 on a 510 x 515 mm panel, and 49 on a 600 x 600 mm panel. TSMC’s CoWoS roadmap aims for 5.5 reticles in 2026, 9.5 in 2027, and 14 reticles in 2028, but Rapidus is pursuing panel-level processing instead of wafer-based scaling.

The strategy is already in development. Rapidus has demonstrated the 600 mm panel format and is working with Lam Research’s Kallisto electroplating system on 2.xD packaging with redistribution layers on 600 mm glass carriers. The company produced its first large-format glass interposer prototype in late 2025, plans mass production in 2028, and has taped out a 2 nm GAA test chip using ASML EUV tools with a claimed transistor density of 237 MTr/mm². Its FY2026 plan brings the Rapidus Chiplet Solutions pilot line into full operation to verify 2.xD and 3D packaging processes.