Qualcomm stacks LPDDR for high-bandwidth AI accelerator memory

Qualcomm announced High Bandwidth Compute, a memory-compute hybrid intended to replace traditional High Bandwidth Memory with higher performance, efficiency, and throughput. The design stacks LPDDR memory across multiple layers in a 3D vertical arrangement and connects them using through-silicon vias, aiming to deliver similar bandwidth and capacity with lower power consumption than conventional DDR-based HBM stacks.

The base of HBC is a compute die that performs near-memory computation and offloads some work from the main processor. Qualcomm’s approach resembles HBM4 designs that use a logic die for functions such as packet tracing and data preparation, but the company is targeting more efficient data movement and a 6x increase in bandwidth per watt compared with the current HBM specification.

HBC Gen 1 achieved 133 TB/s of bandwidth on the AI250 accelerator card, a 18x increase over the LPDDR5X used in Qualcomm’s AI200 card. Qualcomm says the technology has a viable roadmap across many of its AI accelerators, with HBC Gen 1 shipping with the AI250 AI accelerator in mid-2027 and HBC Gen 2 expected to bring further bandwidth gains.